From the beginning of semiconductor device technology, physicists have postulated a host of semiconductor hetercstructures, i.e., combinations of layers of different materials in a single composite crystal. The fascination in this kind of structure is traceable to the large selection of electrical properties thus potentially available to device designers. The early visions of a wide variety of combinations have not yet been realized, and it is now recognized that some semiconductor heterostructures of sufficient crystalline quality for state of the art devices are difficult to produce.
A class of heterostructures comprising a single crystal silicon substrate and an epitaxial metal silicide layer thereon, with epitaxial silicon overlying the silicide layer, has been disclosed in U.S. Pat. No. 4,492,971, and a method for producing such structures is disclosed in U.S. patent application Serial No. 445,014, filed Nov. 29, 1982, both incorporated herein by reference. A ballistic transistor advantageously embodied in a silicon/silicide/silicon heterostructure, with the silicide preferably being cobalt silicide or nickel silicide, is disclosed in U.S. patent application Serial No. 637,061 ('061), filed Aug. 2, 1984, also incorporated herein by reference.
A Semiconductor device, commonly referred to as a permeable base transistor (PBT) was disclosed by C. O. Bozler et al. in U.S. Pat. No. 4,378,629 ('629), also incorporated herein by reference. As described in the '629 patent and in a series of subsequent publications, a PBT comprises a semiconductor substrate, typically GaAs, with a patterned metal (typically W) layer deposited thereon, and with a further semiconductor layer deposited onto the metal layer, with semiconductor material connecting the semiconductor layer to the substrate through apertures etched through the metal layer. The metal layer is patterned by known processes, typically photolithography and subsequent dry etching. Typically, the patterned metal layer comprises metal fingers, with the spaces between the fingers being semiconductor-filled apertures. However, '629 also discloses that other geometries, e.g., comprising holes, are possible, but may not offer the high transconductance-to-capacitance ratio ascribed to the preferred grating structure (see column 14 of '629).
The operation of a PBT is significantly affected by the choice of metal layer thickness and aperture size. As taught by the prior art, the thickness of the metal layer should in the order of 10% of the zero bias depletion width of the semiconductor material, and the width of the slits in the metal layer should be of the order of the zero bias depletion width. For example, for a carrier concentration of 1.10.sup.16 cm.sup.-3 in the substrate material, a grating consisting of 200 .ANG. thick metal fingers of 2000 .ANG. width, separated by slits of 2000 .ANG.width, meets the above criteria.
As can be seen from the above exemplary dimensions, the patterned metal layer has small features indeed, and the production of such a pattern by conventional means is difficult. Furthermore, lithography and etching generally require operations that are not carried out in UHV, resulting in contamination problems. This may increase defect densities.
A metal base transistor of the above described type, i.e., comprising a patterned metal layer comprising a grating, embodied in silicon/silicide/silicon, is disclosed in U.S. Pat. No. 4,488,038. See also A. Ishizaka and Y. Shiraki, Japanese Journal of Applied Physics, Volume 23(7), pp. L499-L501 (1984), where the formation of an embedded monocrystalline NiSi.sub.2 grid in silicon is reported.
The mode of operation of a PBT is well known to those skilled in the art and requires no detailed discussion here. See, for instance, C. O. Bozler et al, IEEE Transactions on Electron Devices, Volume ED-27(6), pp. 1128-1141 (1980), and the '629 patent. Briefly, due to the small width of the slits in the metal layer, there exists a potential barrier in the semiconductor material extending through the slits. The height of this barrier can be varied by means of a voltage applied to the metal layer, whereby the flow of electrons between the semiconductor overlayer and the semiconductor substrate can be changed. One of the semiconductor regions is conventionally referred to as the emitter, and the other as the collector, whereas the metal layer is referred to as the base. For the sake of clarity of exposition, we will herein generally refer to the substrate layer as the collector and to the semiconductor overlayer as the emitter, without thereby foreclosing the possibility of a device in which the active regions are reversed, or which otherwise differs from the conventional three-terminal structure.
As is known to the prior art, a possible base configuration is that of a "grid". The minimum dimension of grid openings typically should not exceed the depletion layer thickness. For most practical doping levels, such openings are too small to be produced conveniently by known methods.
A structure which comprises a metal layer that was said to act similar to a very fine grid is reported in J. Lindmayer, Proceedings of the IEEE, Volume 52, page 1751 (1964). The metal base layer in question was reported to be nonuniform, with current flowing through a large number of thin portions (also referred to as "weak" points) of the polycrystalline base layer. K. Ishibashi et al., Extended Abstracts of the 15th Conference on Solid State Materials, Tokyo 1983, pp. 11-14, disclose that relatively thick (100 nm) CoSi.sub.2 films grown on Si by solid phase epitaxy often are of poor crystalline quality and often "break", exposing the substrate. See, for instance, FIG. 1 of that reference. These authors also give prescriptions for improving the quality of such films. This reference thus exemplifies the proposition that workers in the field have generally directed their efforts towards producing silicide layers of the highest possible perfection.
Because the characteristics of a PBT depend, inter alia, on the size and geometry of the apertures in the base, it would be desirable to have available a lithography-free method, that allows uninterrupted growth of the heterostructure in clean UHV conditions, for producing an appropriately perforated thin silicide layer on Si, with the openings in the layer having a most likely effective diameter of the order of the depletion layer thickness in the semiconductor. This application discloses such a method, and devices produced by the method.